There is a known conventional technology for evaluating the delay characteristics of a circuit by measuring the length of time between when a signal is input to the circuit and when the signal is output from the circuit. An example of such technology is a technology for a delay measuring circuit that inputs a pulse signal to a circuit in which an input signal and an output signal have a one-to-one correspondence with each other and measures the delay time until the input pulse signal is output from the circuit under test.
For example, as illustrated in FIG. 12, the delay measuring circuit includes a delay circuit in which a plurality of delay elements that delay an input pulse signal and then output the input pulse signal are connected in series. Moreover, the delay measuring circuit includes a pulse generator that outputs a pulse signal with a predetermined waveform to the circuit under test and the delay circuit at the same time. Moreover, the delay measuring circuit includes a plurality of FFs (Flip-Flops) 1 to n, each of which receives a pulse signal delayed by the circuit under test and a pulse signal output from a corresponding delay element. Each of the FFs 1 to n is arranged at the subsequent stage of a corresponding delay element. FIG. 12 is a diagram for explaining the delay measuring circuit.
Each of the FFs 1 to n receives a pulse signal that has passed a different number of delay elements and therefore the timing with which the pulse signals are received from the delay elements is different. When each of the FFs 1 to n receives a pulse signal from the delay element to which it is connected before receiving a delayed pulse signal from the circuit under test, each of the FFs 1 to n captures the pulse signal received from the delay element.
In other words, each of the FFs 1 to n is classified as an FF that has captured a pulse signal and an FF that has not captured a pulse signal in accordance with the period of time for which the circuit under test delays a pulse signal. The delay measuring circuit measures the period of time for which the circuit under test delays a pulse signal by determining for each of the FFs 1 to n whether it captures a pulse signal after inputting the pulse signal to the circuit under test and the delay circuit.
Patent Document 1: Japanese Laid-open Patent Publication No. 2010-002222
However, with the technology that inputs the same pulse signal to the delay circuit and the circuit under test described above, only a pulse signal with a predetermined waveform is input to the circuit under test; therefore, there is a problem in that the worst delay, which is the maximum value of the delay time, is not appropriately measured.
For example, the circuit under test has different characteristics in some cases between the case where a signal is input whose logical value changes from a low level to a low level via a high level and the case where a signal is input whose logical value changes from a high level to a high level via a low level. In other words, the circuit under test outputs a signal with a different delay time in some cases depending on the direction in which the input signal changes, i.e., for each of the direction of change from a low level to a high level and the direction of change from a high level to a low level. Therefore, when the delay measuring circuit measures the delay of the input signal in a case where the signal input to the circuit under test changes in one direction, for example, from a low level to a high level, the worst delay is not appropriately measured in some cases.